The on-chip memory (RAM or ROM) content may get corrupted after asynchronous reset. The asynchronous reset assertion to the logic driving the address bus of the FPGA embedded memory can cause asynchronous logic propagation. This can cause multiple address lines into the embedded memory to become asserted simultaneously, which can cause charge sharing between bit cells, corrupting the contents of the embedded memory. The current Qsys reset implementation does not include specific handling logic to protest against such memory corruption issue.
This can cause a functional failure in your design where the memory contents need to be preserved at all time, such as when the on-chip memory is used to store Nios II processor software. If the memory content is corrupted after asynchronous reset, the Nios II processor may stall when executing corrupted instruction code from the memory. The stalled processor is unrecoverable and FPGA reconfiguration is required to fix the problem.
If you encounter similar issue in your system that uses Qsys on-chip memory, you can apply device patch DP2 for Quartus II software version 13.0 to fix the problem. To obtain the patch, visit http://software.altera.com/
This issue will be fixed in future releases of Quartus II software starting with version 13.0 SP1.
This issue affects other Altera intellectual properties (IP) including the Altera UniPHY memory controller and transceiver reconfiguration controller. To learn more, refer to solution rd05212013_358 and rd05022013_457.