Critical Issue
The Stratix V Hard IP for PCI Express User Guide and the Transceiver Reconfiguration Controller IP Core chapter of Altera Transceiver PHY IP Core User Guide should include the following constraint for designs including the Stratix V Hard IP for PCI Express IP Core when CvP is enabled. If your design includes the following components:
- The Stratix V Hard IP for PCI Express with CvP enabled
- Any additional transceiver PHY connected to the same Transceiver Reconfiguration Controller
then you must connect the PLL reference clock which is called refclk
in
the Stratix V Hard IP for PCI Express IP core to the mgmt_clk_clk
signal
of the Transceiver Reconfiguration Controller and the additional
transceiver PHY. In addition, if your design includes more than
one Transceiver Reconfiguration Controller on the same side of the
FPGA, they all must share the mgmt_clk_clk
signal.
No workaround is necessary. This constraint will be documented in future versions of the Stratix V Hard IP for PCI Express User Guide and the Transceiver Reconfiguration Controller IP Core chapter of Altera Transceiver PHY IP Core User Guide.