Article ID: 000079122 Content Type: Troubleshooting Last Reviewed: 04/06/2023

What is the relationship between PHASEDONE and SCANCLK in the ALTPLL Intel® FPGA IP?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

PHASEDONE deassertion (low) is synchronous to SCANCLK rising edge and PHASEDONE assertion (high) is asynchronous to SCANCLK in the ALTPLL Intel® FPGA IP.

Resolution

N/A

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