If you have two PLLs called PLL1 and PLL2 and a free running clock source from pin named sysclk.
If PLL1 uses sysclk to derive 50MHz reconfig_clk and asserts pll1_locked signal after reconfig_clk is stablized.
If PLL2 uses sysclk to generate 125MHz fixedclk and asserts pll2_locked signal after fixedclk is valid.
For PCIe core, the reconfiguration block must be held in reset until both of these clocks are stabled. Therefore, its input offset_cancellation_reset must be set until both pll1_locked and pll2_locked are asserted. Hence, offset_cancellation is the inversion of pll1_locked and pll2_locked.
In Verilog, the logic will look similar to the following:
assign offset_cancellation_reset = !(pll1_locked & pll2_locked);
When reconfiguration block is out of reset, it will start offset_cancellation process to setup RX side of the transceiver and assert "BUSY" flag. When this procedure is completed, the reconfiguration block controller will deassert the BUSY flag.