Why does my Stratix II GX transceiver channel run at an incorrect data rate if it is configured to the SONET OC12 protocol mode?

When you configure a Stratix® II GX transceiver channel in SONET OC12 protocol with a 155.52 MHz clock input from a dedicated refclk pin, the Quartus® II software does not instantiate the required refclk pre-divider to run the channel at the SONET OC12 data rate (622 Mbps). Because the refclk pre-divider is not instantiated, the SONET OC12 channels run at double the data rate (1244 Mbps). 

This problem exists only in the Quartus II software versions 7.0, 7.1, and 7.1 SP1, and is fixed beginning with the Quartus II software version 7.2 .

There are two methods to work around this issue in the Quartus II software versions 7.0, 7.1, and 7.1 SP1, depending on the design. Workaround 1 is for designs that use the dynamic channel and TXPLL  reconfiguration feature (enabled by the Enable channel and TX PLL reconfiguration option in the ALT2GXB MegaWizard® plug-in). Workaround 2 is for designs that use dynamic channel reconfiguration (enabled by the Use alternate reference clock option on the Reconfig page of the ALT2GXB MegaWizard plug-in) or do not use any dynamic reconfiguration.

Workaround 1 - For designs that use the dynamic channel and TXPLL  reconfiguration feature in the Quartus II software versions 7.0, 7.1, and 7.1 SP1.

In the MegaWizard-generated wrapper file for the SONET OC12 protocol alt2gxb instance, modify the enable_pll_inclk<x>_divider parameter (where x is 0,1,2,3 or 4) to true, for the corresponding clock input connected to the refclk pin that provides the155.52 MHz clock frequency. For example, if clock input 1 in the SONET OC12 ALT2GXB MegaWizard instance is connected to the refclk pin providing 155.52 MHz clock, set enable_pll_inclk1_divider to true. This change enables the Quartus II software to create a refclk pre-divider for the clock1 input when you compile the modified alt2gxb instance. 

Change the enable_pll_inclk<x>_divider parameter to true in the alt2gxb MegaWizard-generated wrapper files for all instances that connect to the same 155.52 MHz clock input. For example, if the clock2 input port of any other alt2gxb instance is connected to the refclk pin providing the 155.52 MHz, change the enable_pll_inclk2_divider to true in the corresponding wrapper files.

After you make the above modifications, regenerate the Memory Initialization File (.mif) for all modified instances.

To simulate the design, generate the transceiver model simulation file (.vo for Verilog HDL, .vho for VHDL) with the Quartus II EDA Netlist Writer instead of using the alt2gxb MegaWizard plug-in. You must use the EDA Netlist Writer because the functional simulation model generated by the alt2gxb MegaWizard plug-in does not include the enable_pll_inclk<x>_divider parameter. The EDA Netlist Writer creates the refclk pre-divider in the simulation model file (.vo or .vho). Use the following steps to generate the simulation model file:

1. On the Assignments menu, choose Settings.
2. Under EDA Tool Settings, choose Simulation.
3. Select the Tool name for your third-party simulation tool.
4. In the Format for output netlist list, select VHDL or Verilog based on your requirements.
5. In the Output directory field, specify the directory for the .vo or .vho file.
6. Click More Settings and set Generate netlist for functional simulation only to On.
7. Compile the top-level module of your design that contains the alt2gxb and the alt2gxb_reconfig instances.
8. Note: You must connect the reconfig_fromgxb and reconfig_togxb ports between the alt2gxb and the alt2gxb_reconfig instances. Otherwise, the Quartus II software removes these ports, and the generated .vo or .vho simulation model file does not work as expected.

Workaround 2 - For designs that use dynamic channel reconfiguration or do not use any dynamic reconfiguration, in the Quartus II software versions 7.0, 7.1, and 7.1 SP1.

Add the following Verilog code to your design to add the refclk pre-divider. Connect the input port of the refclk pre-divider instance to the refclk pin that provides 155.52 MHz clock input. Connect the output port to all alt2gxb instances that use this 155.52 MHz clock input.

//refclk divider Verilog code for Workaround 2

module my_refclk_div(in, out);
input in;
output out;
    stratixiigx_hssi_refclk_divider my_refclk_divider (
       .inclk(in),
       .clkout(out));
    defparam my_refclk_divider.enable_divider = "true";
    defparam my_refclk_divider.divider_number = 0;
    defparam my_refclk_divider.refclk_coupling_termination = "normal_100_ohm_termination";
endmodule

If  your design has any other transceiver channel instance that uses the 155.52 MHz clock input from the same refclk pin as the SONET OC12 alt2gxb instance, change the What is the input clock frequency? setting to 77.76 MHz on the General page of the alt2gxb MegaWizard plug-in.

This step is required because any channel that uses the same 155.52 MHz clock input receives only a 77.76 MHz input reference clock frequency when the refclk pre-divider is added to the clock path. For example, if you have configured any channel in BASIC mode to run at 2488 Mbps using the same 155.52 MHz clock input, set the What is the input frequency? to 77.76 MHz.

If the channel reconfiguration feature is enabled, regenerate the Memory Initialization File (.mif) for all modified instances.

You can use the simulation model files (.vo or .vho) generated by the ALT2GXB MegaWizard plug-in to simulate the design.