Article ID: 000078747 Content Type: Troubleshooting Last Reviewed: 06/04/2014

Why does the JTAG IDCODE read fail, when performing boundary scan of an Arria II, Arria V, Stratix III, Stratix IV or Stratix V device, with a pre-configuration BSDL file?

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BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description When using a pre-configuration BSDL file, boundary scan should be perfomed with the nCONFIG pin pulled low. However, when the nCONFIG pin is pulled low, the device JTAG IDCODE that is read from the device may not match the one stored in the BSDL file.
Resolution The JTAG IDCODE read should be performed when the nCONFIG (and nSTATUS) pins are high. Alternatively, use a post-configuration BSDL file, where it is requirement for nCONFIG to be high, when performing boundary scan.

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Related Products

This article applies to 9 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® IV E FPGA
Stratix® V GX FPGA
Arria® V GX FPGA
Arria® II GX FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs

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