Critical Issue
The Nios II Development Kit version 5.0 and later includes
a CompactFlash controller peripheral suitable for interfacing to
CompactFlash cards in True IDE mode on Nios development boards.
For True IDE mode to operate, CompactFlash cards require that the ATASEL_N
input
be driven to ground during power-up.
The CompactFlash controller peripheral includes a configurable
power register, used to cycle power to CompactFlash cards from Nios
II software through a metal oxide semiconductor field-effect transistor
(MOSFET) on the Nios development boards. However, in certain development
boards, power to the CompactFlash card does not turn off completely
during this power cycle operation. Because of this condition, the CompactFlash
might not sample the ATASEL_N
pin during the power-cycle
operation after FPGA configuration when this pin is driven to ground.
Instead, the CompactFlash card might sample the ATASEL_N
pin
when power is first applied to the development board, when I/O is
not yet driven by the FPGA (before FPGA configuration).
If you encounter errors with CompactFlash when using the Nios development boards, try one of the following solutions:
- Use a different CompactFlash card. Certain cards are more susceptible to the power-cycling issue than others.
- Modify the Nios development board. This is recommended if
you are familiar and comfortable with board-level modifications.
Disconnect pin 9 (
ATASEL_N
) on the CompactFlash socket on your Nios development board and tie this pin to ground.
The CompactFlash socket uses a staggered numbering on the pins (starting from pin 1: 1, 26, 2, 27, ...); refer to the CompactFlash Association specification for right-angle surface-mount connectors for exact specifications on this connector. This modification permanently enables True IDE mode operation.