In the Quartus® II software version 12.0SP2, DQS tracking is enabled for DDR3 controllers operating above 533MHz in Stratix® V and 450MHz in Arria® V. When DQS tracking is enabled, a sequencer tracking manager (sequencer_trk_mgr.sv) is created to control the tracking.
There is a problem in the sequencer_trk_mgr.sv file where the cfg_num_dqs signal is only 3 bits and can support up to 7 DQS groups. For DDR3 interfaces that are 64-bit (8 DQS groups) or 128-bit (16 DQS groups), the sequencer track manager will lock up, causing the Avalon bus-ready signal avl_ready to be stuck low.
This problem has been fixed in Intel® Quartus® Prime Software version 12.1.