Article ID: 000078453 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my Stratix V PLL simulate incorrectly when using models created in the Quartus II software version 11.1sp2 or earlier?

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 11.1 SP2 and earlier, incorrect Stratix® V PLL simulation models may cause the PLL output frequency to show higher than expected output frequency value if you have two or more independent Altera_PLL megafunctions in your testbench.

    Resolution

    This problem is fixed beginning with the Quartus II software version 12.0.

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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