Description
The UniPHY-based memory interface IP cores are delivered with both the PHY and the controller integrated. In Quartus® II design software versions 10.0 SP1 and earlier versions, there is no MegaWizard option to instantiate the UniPHY PHY standalone for use with a custom controller. However, you can replace the Altera High-Performance memory controller with a custom memory controller by following the outlined procedure.
- Parameterize and generate your variation of the UniPHY-based memory controller IP.
- This will generate a top-level HDL file called <variation_name>.v or .vhd, and a sub-directory named <variation_name> .
- The top-level module instanties the <variation_name>_controller_phy module. This module is located in the <variation_name>/ rtl directory and in-turn instantiates the PHY and controller.
- Controller module is named : <variation name>_alt_ddrx_controller
- PHY module is named : <variation name>_memphy_top
- The generated pin and timing constraint scripts require the design hierarchy to be maintained.
- Open the <variation_name>/ rtl/<variation_name>_controller_phy.sv file.
- Replace the <variation name>_alt_ddrx_controller module with your custom controller module.
- Delete the ports of the Altera High-Performance memory controller, and add the top-level ports of your custom controller.
- Similarly, update the port names in top-level module in the <variation_name>.v or .vhd file.
- Compile and simulate the design to ensure functionality.
- Note that regenerating the UniPHY memory interface IP will erase all modifications made to the HDL files. And the parameters you select in the MegaWizard are stored in the top-level <variation_name> module. Hence, the steps above must be repeated everytime the IP variation is regenerated.