Article ID: 000078237 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Can I use a transceiver RX Pin as a CDR REFCLK for the HDMI Design Example Receiver Interface (Sink) on Arria® 10 and Cyclone® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    No, you cannot use a transceiver RX Pin as a CDR REFCLK for the HDMI™ Design Example Receiver Interface (Sink) on Arria® 10 and Cyclone® 10 devices.

    The HDMI TMDS_CLK frequency is dependent on the video resolution. Low resolutions have a TMDS_CLK frequency of 27MHz below the minimum CDR REFCLK frequency. The HDMI Design Example implements a cascaded IOPLL architecture to multiply up the TMDS_CLK for low-resolution video.

    TMDS_CLK -> IOPLL -> CDR REFCLK

    The RX Pin as a REFCLK feature can only be used when connected directly to the CDR REFCLK. Your design will fail to fit in the Intel® Quartus® Prime Software if you place the HDMI Design Example RX REFCLK on an Rx Pin.

    Resolution

    To work around this problem you should place your HDMI Design Example TMDS_CLK on a dedicated transceiver REFCLK pin.

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA