PHY Clock Tree Not Driven by Optimal PLL Output Counters

This problem affects DDR2 and DDR3, LPDDR2, QDR II, and RLDRAM II products.

External memory interfaces targeting Arria V devices, whose PHY clock tree is not driven by counters 0-3 or counters 14-17 may fail to meet timing.

The workaround for this issue is to use a QSF assignment to constrain the PLL output counters, as follows:

set_location_assignment <PLL counter location> -to <PLL output signal>

To find <PLL counter location> and <PLL output signal> follow these steps:

1. Compile the design in the Quartus II software.
2. Find the PLL using the Find or Netlist Navigator tools in the RTL Viewer.
3. Open the design in the RTL Viewer.
4. Right-click the required GENERIC_PLL instance and choose Locate in Chip Planner from the Locate menu.
5. The Chip Planner displays a PLL output counter where is generic PLL instance is placed. Select the PLL output counter to see its properties, modes, and values in a Node Properties window.
6. PLL output signal is the value for the full name property, and the value for the location property is the PLL counter location for the currently used counter. Find the desired PLL counter location. The PHY clock must be driven by counters 0-3 or 14-17, which are always the top-four or bottom-four counters in the floorplan, depending on the orientation of the FFPLL. Only one of two counters can drive each input of the PHY clock tree:

For best performance, the PHY clock should be driven by either counters 0-3 or counters 14-17. You may have to change the selected elements from FFPLL_* to PLLOUTPUTCOUNTER_* to see the PLL counter location for each counter.

The following illustrates an example QSF assignment:

set_location_assignment PLLOUTPUTCOUNTER_X81_Y91_N1 -to qdrii_example|dut_if0:if0|dut_if0_pll0:pll0|pll_mem_phy_clk �

This issue will be fixed in a future version.