Article ID: 000078052 Content Type: Troubleshooting Last Reviewed: 02/13/2006

What are the set-up and hold time requirements associated with the enable signal of a logic element (LE) or Macrocell register relative to the clock for APEX™ 20K, FLEX® 10K, MAX® 9000, and MAX 7000 device families?

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Description The setup and hold times at the register for data relative to the clock also apply for the enable signal relative to the clock. You must setup the enable signal for a time period of tSU and hold the enable signal for a time period tH relative to the clock. This is true for LE registers, macrocell registers, Fast I/O registers, and I/O cell registers. tSU and tH values for a specific APEX 20K, FLEX 10K, MAX 9000, or MAX 7000 device are found in their respective data sheets.

This solution does not apply to FLEX 8000, FLEX 6000, or MAX 5000 devices since they do not have dedicated clock enables on their registers.

  For the APEX 20K, FLEX 10K, MAX 9000, and MAX 7000 family data sheets, see the Altera web site.

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Intel® Programmable Devices