Article ID: 000078004 Content Type: Error Messages Last Reviewed: 11/13/2018

Error May Occur When Simulating VHDL Designs With MMR Enabled Using VCS-MX

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    A segmentation fault may occur when simulating an Arria 10 EMIF IP in VHDL with MMR enabled, using Synopsys VCS-MX.

    Resolution

    The workaround for this issue is as follows:

    1. Run vhdlan without the -xlrm option.
    2. Run vcs with the -xlrm option.

    This problem will be fixed in a future version.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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