Article ID: 000078002 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Under what conditions might the Deterministic Latency PHY fail to achieve rx_syncstatus when implementing the OBSAI protocol in Arria® V GX/GT devices?

Environment

  • Quartus® II Software
  • Arria® V Transceiver Native PHY Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When implementing the OBSAI protocol using the Deterministic Latency PHY in Arria® V GX/GT devices, you may fail to achieve rx_syncstatus when IDLE, IDLE_ACK, and IDLE_REQ patterns are sent during the link-up process.  

    Resolution

    You can achieve synchronization by retriggering rx_patternalign or asserting rx_digitalreset.

    This applies to the Deterministic Latency PHY with the following configuration.

    • Data Rate: 6.144 Gbps
    • PMA-PCS Data Width: 20-bits

    Related articles

    Related Products

    This article applies to 3 products

    Arria® V GX FPGA
    Arria® V GT FPGA
    Arria® V FPGAs and SoC FPGAs

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