Article ID: 000077972 Content Type: Troubleshooting Last Reviewed: 07/25/2023

Are there any updates to the 10GBASE-KR PHY IP core in Quartus® II software version 13.0 SP1 dp1?

Environment

  • Quartus® II Subscription Edition
  • Ethernet
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In certain high error conditions, the 10GBASE-KR PHY IP core link training algorithm selects a post-tap value that is too low.

     

     

    Resolution

    Install the Quartus® II software 13.0 SP1 dp1 patch.  Regenerate the 10GBASE-KR PHY IP core and recompile the design. 

    This problem is fixed in the Intel® Quartus® II software version 14.1

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    This article applies to 4 products

    Stratix® V FPGAs
    Stratix® V GX FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA

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