Description
In the Cyclone V device handbook, Hard Processor System Technical Reference Manual, SDRAM PLL output clocks are notlisted in the Table 2-6. The maximum frequency of each clocks depend on the speed grade of the device and you can refer to the table below.
Clk name / device speed grade | C6 | C7, I7 | C8, A7 |
ddr_dqs_base_clk | up to 533 MHz | up to 533 MHz | up to 400 MHz |
ddr_2x_dqs_base_clk | up to 1066 MHz | up to 1066 MHz | up to 800 MHz |
ddr_dq_base_clk | up to 533 MHz | up to 533 MHz | up to 400 MHz |
Resolution
The frequency range will be included in the future release of the Handbook.