Article ID: 000077565 Content Type: Error Messages Last Reviewed: 03/04/2013

Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_lvds_cv.cpp, Line: 2420

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 12.0, you may see this internal error if your design implements an ALTLVDS_TX megafunction with the tx_outclock signal driving core logic. This internal error occurs for designs targeting Arria® V or Cyclone® V devices.

    Resolution

    Using the tx_outclock signal to drive core logic is unsupported.

    The Quartus II software begining with version 12.1 reports an error message describing the problem instead of producing an internal error.

    Related Products

    This article applies to 5 products

    Cyclone® V GX FPGA
    Cyclone® V GT FPGA
    Cyclone® V E FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA

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