Why can't I see 25Gbps Ethernet transceiver channels in the Transceiver Toolkit for Intel® Stratix10® H-Tile production device if my design includes the 25G Ethernet Intel FPGA IP? 

Due to the auto adaptation module finite state machine(FSM) in the 25G Ethernet Intel FPGA IP if you turn on the Enable auto adaptation triggering for RX PMA CTLE/DFE mode option during the IP generation, the Transceiver Toolkit operation will be interrupted when the FSM turns on and off background calibration on H-tile production device. Thus you will not see the channel appear in Transceiver Toolkit. For device without background calibration like L-tile production device, the auto adaptation module FSM doesn't contain states to turn on and off background calibration. It will not be affected by this issue.

First workaround: Turn off the Enable auto adaptation triggering for RX PMA CTLE/DFE mode option to workaround this problem.

Second workaround: If you enabled the Enable auto adaptation triggering for RX PMA CTLE/DFE mode, write 1'b1 to bit[0] of 0x343 register to hold the auto adaptation module FSM to an idle state before you launch the Transceiver Toolkit so that the transceiver channel appears in the Transceiver Toolkit. Close the Transceiver Toolkit before you write 1'b0 to bit[0] of 0x343 register to re-start the auto adaptation module FSM so that the System Console doesn't hang.

Below are steps you should follow if you use Intel® Stratix10® 25G Ethernet Intel FPGA IP Design example and target Intel® Stratix10® H-tile production device and “Enable auto adaptation triggering for RX PMA CTLE/DFE mode” option is turned on.

1. In system console, type cd hwtest to navigate to the TCL scripts folder.
2. Type source main.tcl to load the main.tcl file.
3. For single channel design example, type reg_write 0x343 0x1 to hold the auto adaptation module FSM in idle state.
4. For multi-channels design example,
   • type reg_write 0x343 0x1 for channel 0
   • type reg_write 0x10343 0x1 for channel 1
   • type reg_write 0x20343 0x1 for channel 2
   • type reg_write 0x30343 0x1 for channel 3
5. Launch the Transceiver Toolkit, then you will see the 25Gbps transceiver channels.

Follow these steps after you have used the Transceiver Toolkit:

1. Close the Transceiver Toolkit.
2. For single channel design example, type reg_write 0x343 0x0 to re-start the auto adaptation module FSM.
3. For multi-channels design example,
   • type reg_write 0x343 0x0 for channel 0
   • type reg_write 0x10343 0x0 for channel 1
   • type reg_write 0x20343 0x0 for channel 2
   • type reg_write 0x30343 0x0 for channel  3

Both the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide UG-20109 and 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide UG-20110 are updated  to include these additional steps for using Transceiver Toolkit on H-Tile production device when Enable auto adaptation triggering for RX PMA CTLE/DFE mode option is turned on in the Intel® Quartus® Prime Pro Edition Software version 20.1.