When you design your customer's BSP target to Stratix® 10 device in Quartus®II 18.0 and Intel FPGA SDK for OpenCL™ 18.0, you might get the following internal error during base compilation.
Internal Error: Sub-system: CONSTRA, File: /quartus/db/constra/constra_mvsat_bcm_solver.cpp, Line: 523
Could not find a solution for hssi_0_0__z1501a,hssi_0_0__z1545a,hssi_0_1__z1501a,hssi_0_1__z1545a,hssi_1_0__z1501a,hssi_1_0__z1545a,hssi_1_1__z1501a,hssi_1_1__z1545a,hssi_2_0__z1501a,hssi_2_0__z1545a,hssi_2_1__z1501a,hssi_2_1__z1545a,maib_ss_lib_r0_c2,maib_ss_lib_r0_c274,maib_ss_lib_r144_c2,maib_ss_lib_r144_c274,maib_ss_lib_r288_c2,maib_ss_lib_r288_c274
::
maib_ss_lib_r0_c2.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_dll == TX_DLL_DISABLE || hssi_0_0__z1545a.is_active == FALSE || hssi_0_0__z1545a.u_c3aibadapt_wrap_7.xaibcr3_top_wrp.xaibcr3_top.xtxdatapath_tx.op_mode == TX_DLL_ENABLE
maib_ss_lib_r0_c2.x0.u9_2.hdpldadapt.hdpldadapt_tx_chnl.tx_dll == TX_DLL_ENABLE
hssi_0_0__z1545a.is_active == TRUE
hssi_0_0__z1545a.u_c3aibadapt_wrap_7.xaibcr3_top_wrp.xaibcr3_top.xtxdatapath_tx.op_mode == PWR_DOWN
Stack Trace:
This is a bug in Quartus II 18.0 and has been fixed in Quartus II 18.0.1.