Article ID: 000077314 Content Type: Troubleshooting Last Reviewed: 11/29/2024

To save power when the transceiver channels are not in used, can I keep the transceiver channels in the Stratix®10 L- or H-Tile design in reset ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • L-Tile H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    No. Keeping the transceiver channels in analog reset for a long interval will cause performance degradation.

    Resolution

    There is currently no plan to fix this problem. 

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA

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