Article ID: 000077245 Content Type: Troubleshooting Last Reviewed: 01/14/2013

Why does the "Actual Phase Shift" not show the expected value that I set in the Altera_PLL megafunction?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to an issue in the Quartus® II software, the phase shift that you set in the Altera_PLL megafunction may not be your desired value.

    This only occurs with certain multiply and divide factors.  When this does occur, the actual phase shift will be shown as 0ps in the megafunction.

    Resolution

    To workaround this issue, you can manually change the "phase_shift" value in the generated <user_define_ip_name>_0002.v file.

    Find the .phase_shift<clock output number>("0 ps") parameter and change the value to your desired phase shift value.

    For example, if you wish to set a 1200ps phase shift value on clock output 0 (C0), you would change the parameter as shown below:

     .phase_shift0("0 ps"), // original value

     .phase_shift0("1200 ps"), // modified value

    This is scheduled to be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 11 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
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    Arria® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Arria® V GT FPGA
    Arria® V ST SoC FPGA
    Cyclone® V E FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA

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