Article ID: 000077239 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Which clock resources can be driven by the PLL output counters in Stratix III and Stratix IV devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In Stratix® III and Stratix IV devices, the PLL output counters can access global and regional networks as shown in the respective device handbooks.  Note, global networks can only be accessed from PLL output counters C0-C3.  All PLL output counters can access regional networks.

Tables 6-8 and 6-9 show the global and regional connectivity in Clock Networks and PLLs in Stratix III Devices (PDF).

Tables 5-5 and 5-6 show the global and regional connectivity in Clock Networks and PLLs in Stratix IV Devices (PDF). 

Related Products

This article applies to 4 products

Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® IV GX FPGA
Stratix® III FPGAs

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