Description
Due to a problem in the Quartus® II Software v12.0 and earlier, the PLL Intel® FPGA IP does not support negative phase shift entry.
Resolution
To achieve an equivalent phase shift, add one clock cycle (360°) to any required negative phase shift so the result is a positive phase value.
This problem is fixed starting with the Quartus® II Software v12.1 where the PLL Intel FPGA IP supports negative phase shift entry.