How do I implement ALTLVDS in External PLL mode for Stratix® V, Arria® V, and Cyclone® V devices?

The ALTLVDS_RX and ALTLVDS_TX Intel® FPGA IP cores began supporting the External PLL mode option in the Quartus® II software version 11.0 for Stratix® V devices.  The following instructions apply to Stratix V,Arria® V, and Cyclone® V devices. 

The PLL Intel® FPGA IP output clock phase shifts and duty cycles are going to depend on the data rate and deserialization / serialization factor of the interface.  The examples below set the phase shift assuming the clock and data are edge aligned at the pins of the device. 

The PLL Intel FPGA IP clocking requirements for ALTLVDS_TX and ALTLVDS_RX when not using DPA and soft-CDR mode:

• C0:
  • Frequency = data rate
  • Phase shift = -180 360 degrees
  • Duty cycle = 50%
  • Connects to the tx_inclock port of ALTLVDS_TX, and the rx_inclock port of ALTLVDS_RX
• C1:
  • Frequency = data rate / serialization factor
  • Phase shift = [(serialization factor -2) / serialization factor] * 360 degrees
  • Duty cycle = 100 / serialization factor
  • Connects to the tx_enable port of ALTLVDS_TX, and the rx_enable port of ALTLVDS_RX
• C2:
  • Frequency = data rate / serialization factor
  • Phase shift = [(-180 / serialization factor) 360 degrees]
  • Duty cycle = 50%
  • Used as the coreclock for the parallel data registers for both TX and RX, and connects to the rx_syncclock port of ALTLVDS_RX (only when rx_syncclock is required by the receiver)

PLL Intel FPGA IP clocking requirements for ALTLVDS_RX when using DPA and soft-CDR mode (does not apply to Cyclone V devices):

• C0 - C2 are the same as when not using DPA or soft-CDR mode
• C3 is a duplicate of the C0 settings and connects to the rx_dpaclock input port of ALTLVDS_RX

The locked output port of PLL Intel FPGA IP must be inverted and connected to the pll_areset port of the ALTLVDS_RX Intel FPGA IP when using DPA and soft-CDR modes.

For other clock and data phase relationships, Intel recommends that you first instantiate your ALTLVDS_RX and ALTLVDS_TX interface without using the external PLL mode option, compile the megafunction(s) in the Quartus II software, and note the frequency, phase shift, and duty cycle settings for each clock output.  These are listed in the Compilation => Fitter => Resource Section => PLL Usage Summary report.  Enter these settings in the PLL Intel FPGA IP and then connect the appropriate outputs to the ALTLVDS_RX and ALTLVDS_TX Intel FPGA IP cores.