Why are some pins in the M256 package of MAX II devices located in bank 1 (side bank) designated as EDGE_TOP instead of EDGE_LEFT in Quartus II software?

Some pins in the M256 package of MAX® II devices located in bank 1 (side bank) are designated as EDGE_TOP instead of EDGE_LEFT in Quartus® II software because these pads are “logically” located on the top of the chip even though they are “physically” located on the left hand side of the device. 

This means those pins are powered by VCCIO of bank 1, but they enter the core routing fabric through the Vertical IO interface blocks (top of the core). In Quartus II software, the location of the pin is defined by the side of the core it interfaces to, not by the side it is physically placed.

The affected pins in M256 package are pins C1, C2, D1, D2, D3 and E3. This applies to the Max II, MAX IIG, and MAX IIZ devices.