Quartus® II software reports this fitter error when you make an incorrect nPERSTL* pin to PCI Express Hard IP location assignment in Cyclone® V devices.
Pin nPERSTL0 is associated with the upper left PCI Express(PCIe) Hard IP block, and nPERSTL1 is associated with the bottom left PCIe HIP block.
Note: This mapping is opposite to that used by Stratix® V and Arria® V.
To work around this problem modify the RTL as described below, or upgrade to Quartus II software version v13.1
Below are the steps to switch to Soft Reset Controller:
1) Open the .v file in which altpcie_cv_hip_ast_hwtcl is instantiated (e.g. ...\pcie_lib\top.v)
2) Search for the parameter hip_hard_reset_hwtcl and change its value to 0 (zero).
3) Disable pin_perst input port on the IP instance to hardwire pin_perst to 1’b1 (e.g. <project_dir>\top_hw.v).
- Example: .pcie_rstn_pin_perst (1\'b1)
4) Keep driving npor input with original reset signal to reset the core and application logic.