When using the altclkcntrl megafunction in Quartus® II software for Cyclone® III devices, you need to follow these rules to properly connect different clock resources to the clock control block:
- Dedicated clock input pins are allowed on inclk0x and inclk1x
- PLL output clocks are allowed on inclk2x and inclk3x
- Lower numbered clock resources connect to lower numbered inclkx ports on the clock control block (see examples below)
- Higher numbered clock resources connect to higher numbered inclkx ports on the clock control block (see examples below)
Use Table 6-2 from Clock Networks and PLLs in Cyclone III Devices (PDF) to understand the legal input resources for each global clock network.
Example 1:
Global clock network G0 can accept dedicated clock pins CLK0 and CLK3, as well as PLL1 output clocks C0 and C2. The following port mapping is required (inclkx ports can be left unconnected if you are not using the input resource associated with that input port on the clock control block):
- CLK0 - inclk0x (low numbered dedicated clock input to the low order inclk port that accepts clock pins)
- CLK3 - inclk1x (high numbered dedicated clock input to the high order inclk port that accepts clock pins)
- C0 - inclk2x (low numbered PLL output clock to the low order inclk port that accepts PLL outputs)
- C2 - inclk3x (high numbered PLL output clock to the high order inclk port that accepts PLL output)
Example 2:
Global clock network G2 can accept dedicated clock pins CLK0 and CLK1, as well as PLL1 output clocks C2 and C4. The following port mapping is required:
- CLK0 - inclk0x (low numbered dedicated clock input to the low order inclk port that accepts clock pins)
- CLK1 - inclk1x (high numbered dedicated clock input to the high order inclk port that accepts clock pins)
- C2 - inclk2x (low numbered PLL output clock to the low order inclk port that accepts PLL outputs)
- C4 - inclk3x (high numbered PLL output clock to the high order inclk port that accepts PLL output)
Notice C2 connects to inclk3x on the clock control block for the global 0 network, but connects to inclk2x on the clock control block for the global 2 network. This is because on the global 0 network C2 is the higher numbered PLL output clock that connects to this clock resource while C2 is the lower numbered PLL output clock that connects to the global 2 clock resource.
You can assign clock control blocks to specific clock resources by applying location assignmets to them using the Assignment Editor in the Quartus II software. The value field to represent a global clock network is "CLKCTRL_Gx" where x is the global clock network number. For Cyclone III devices, it can be an integer value between 0 and 19 (see Table 6-2 for available clock networks per device density).