Article ID: 000077098 Content Type: Troubleshooting Last Reviewed: 06/25/2014

Do I need to setup the Avalon-MM-to-PCI Express address translation tables when using 64-bit addressing for the Avalon-Memory Mapped Hard IP for PCI Express?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Avalon-Memory Mapped Hard IP for PCI Express® supports 64-bit addressing. If you select 64-bit addressing, no address translation is necessary.
    As a consequence, the 'Avalon to PCIe Address Translation Settings' section of the GUI in Qsys disappears automatically after setting 'Avalon-MM address width' to 64-bit.

    Avalon-MM-to-PCI Express address translation tables in Control Register Access (CRA) space at address 0x1000–0x1FFF are not necessary for 64-bit addressing.

    Resolution

     

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA

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