The Quartus® II software reports the lock range of each PLL used in the design (see related solution below). However, there are sometimes small rounding errors when calculating the VCO frequency based on the PLL parameters (see related solution below). If the input clock frequency to the PLL is very close to the lock range limit, then the Compilation Report may indicate the lock range is beyond the input clock frequency, even though there are no errors or warnings during the compilation.
You can manually calculate the lock range of the PLL using the following equations:
Fin min = VCO min frequency x N / M x K
Fin max = VCO max frequency x N / M x K
Where:
Fin = PLL input reference clock frequency
VCO min frequency = see device Datasheet
VCO max frequency = see device Datasheet
N = N counter setting for your PLL
M = M counter setting for your PLL
K = VCO post scale counter setting for your PLL
For Stratix® II, Stratix II GX, and HardCopy® II devices, there is an additional rule that the minimum frequency at the phase frequency detector (PFD) must be at least 8 times the maximum bandwidth frequency. The PFD frequency is calculated using the following equation:
Fin(PFD) = Fin / N
The bandwidth frequency range is reported in the Compilation Report => Fitter => Resource Section => PLL Summary.
If your input clock frequency is within the lock range determined by the manual calculation, then this will explain why you do not have any warnings or errors for your PLL in the Quartus II software. If you do receive a warning or critical warning in the Quartus II software which indicates your input clock is not within the valid lock range of the PLL, then the PLL may not be able to lock. Here is an example of a related critical warning:
Critical Warning: Input frequency of PLL "<PLL instance>" must be in the frequency range of <Freq min> to <Freq max> for locking
For further information, go to Phase-Locked Loop Basics, PLL.