Why does the Intel® Arria® 10 and the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design report ignored SDC constraint warnings?

When compiling the Intel® Arria® 10 or the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design generated using Intel® Quartus® Prime Software version 19.4 or earlier, the following ignored SDC constraint warnings will be seen.

Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(63): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n could not be matched with a pin 

Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(53): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n could not be matched with a pin 

Warning(332049): Ignored set_max_skew at altera_pci_express.sdc(34): Argument -to with value [get_registers {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_data_reg[*] *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_datak_reg[*]}] contains zero elements               

Warning(332049): Ignored set_max_skew at altera_pci_express.sdc(35): Argument -to with value [get_registers {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_data_reg_1[*] *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_datak_reg_1[*]}] contains zero elements               

Warning(332049): Ignored set_max_delay at altera_pci_express.sdc(37): Argument is an empty collection 

Warning(332174): Ignored filter at altera_pci_express.sdc(38): *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:rx_polinv_dbg.dbg_rx_valid_altpcie_sc_bitsync_1|altpcie_sc_bitsync:altpcie_sc_bitsync|altpcie_sc_bitsync_meta_dff[0] could not be matched with a clock or keeper or register or port or pin or cell or partition 

Warning(332049): Ignored set_false_path at altera_pci_express.sdc(38): Argument is not an object ID 

Warning(332174): Ignored filter at altera_pci_express.sdc(39): *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:rx_polinv_dbg.dbg_rx_valid_altpcie_sc_bitsync|altpcie_sc_bitsync:altpcie_sc_bitsync|altpcie_sc_bitsync_meta_dff[0] could not be matched with a clock or keeper or register or port or pin or cell or partition 

Warning(332049): Ignored set_false_path at altera_pci_express.sdc(39): Argument is not an object ID 

These SDC constraint warnings can be ignored. 

User can safely ignore these SDC constraint warnings