Article ID: 000076993 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Why doesn’t the Intel® Arria® 10 EMIF Debug Toolkit report the AC Calibration Margin?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There’s no Address/Command (AC) calibration margin reported in the Intel® Arria® 10 EMIF Debug Toolkit if either one of the 2 conditions below occur.

    1. Under the Diagnostics tab of the Intel Arria 10 EMIF IP, the "Skip address/command leveling calibration" option is enabled.

    2. Under the Memory tab of the Intel Arria 10 EMIF IP, the “Bank group width" parameter is set to 1.

    The Address/Command calibration margin is reported if the "Skip address/command leveling calibration" option is disabled and the “Bank group width" parameter is set to a value greater than 1.

    Resolution

    The Address/Command calibration margin is reported if the "Skip address/command leveling calibration" option is disabled and the “Bank group width" parameter is set to a value greater than 1.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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