Article ID: 000076926 Content Type: Product Information & Documentation Last Reviewed: 03/19/2015

How do I enable autonomous Hard IP in my Arria V or Cyclone V design using Quartus II version 13.1 and earlier?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    To enable autonomous Hard IP(HIP) in your Arria® V or Cyclone® V design using Quartus® II software version 13.1 and earlier, follow the workaround/fix steps below:

    Ensure that your device has a die revision capable of autonomous HIP.  For detail, refer to the Configuration via Protocol section of your target device Errata Sheet in the following link.

    http://www.altera.com/literature/lit-es.jsp

    Resolution

    Create a quartus.ini file that include the below settings in the INI file. This quartus.ini file should be save in the quartus project directory. If you already have a quartus.ini file, add the below settings to it.

    PGMIO_ENABLE_AUTONOMOUS_HIP_MODE=ON
    PGMIO_DISABLE_AV_CV_AUTONOMOUS=OFF

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    This article applies to 8 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Arria® V GT FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V SX SoC FPGA

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