Unlike the APEX™ FPGA families that were limited by current sinking between two GNDIO pads, in Stratix devices, the current limitation applies for I/O pins with respect to other I/O pins. Altera recommends a maximum of 200 mA for thermally enhanced cavity down packages and 150 mA for wire-bond packages for 10 adjacent pins as stated in the Using Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook. The Quartus® II software also checks for this limit, and may return a no-fit when your pin assignments exceed the current limit.
For example, if you have 10 GTL output pins in one bank of an FineLine BGA™ package, you need to spread the pins such that when you pick any 10 adjacent pins, there are only six GTL outputs in that group. The calculation is as followed:
Number of GTL outputs per 10 adjacent pins
= 200 mA allowed per 10 adjacent pins/34 mA per pin for GTL output
= 6 pins
Table 1 shows one pin configuration for your design.
| Table 1. I/O Pin Designations | |
| Pin Number | Pin Designation |
| 1 | GTL |
| 2 | GTL |
| 3 | GTL |
| 4 | GTL |
| 5 | GTL |
| 6 | GTL |
| 7 | (1) |
| 8 | (1) |
| 9 | (1) |
| 10 | (1) |
| 11 | GTL |
| 12 | GTL |
| 13 | GTL |
| 14 | GTL |
| 15 | GTL |
| 16 | GTL |
Note to Table 1:
(1) These pins are either unassigned pins or inputs.