Should CONF_DONE and INIT_DONE assert high during Intel® Stratix® 10 FPGA JIC file programming with the Intel® Quartus® Prime Pro Edition Software v18.0?

No, the CONF_DONE and INIT_DONE signals should not assert high during Intel® Stratix® 10 FPGA JIC file programming. 

When using the Intel® Quartus® Prime Pro Edition Software v18.0 to configure an Intel® Stratix® 10 device with the helper image (Factory default SFL image) during the JIC file programming process, you might observe unexpected CONF_DONE and INIT_DONE signals assertion. The helper image (Factory default SFL image) only contains firmware data and not the full configuration data. Thus, the Intel® Stratix® 10 device is only configured with the firmware data and even though the CONF_DONE and INIT_DONE signals are asserted high, the Intel® Stratix® 10 device has not entered the user mode.

In the Intel Quartus Prime Pro Edition Software v17.1 and earlier, the CONF_DONE and INIT_DONE signals are expected to be asserted high as the helper image (Factory default SFL image) contains full configuration data.

This invalid CONF_DONE and INIT_DONE state will not cause any JIC programming failure.

This is fixed in the Intel Quartus Prime Pro Edition Software v21.4 and above.