Description
Yes, due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 17.1 and earlier, 3V I/Os in Intel® Stratix® 10 FPGAs might drive out a strong HIGH during configuration when the pins are assigned as outputs in your compiled design.
This behaviour is not seen when the 3V I/Os are assigned as inputs or bidirectional I/Os.
These 3V I/Os are located in I/O banks 6A,6B,6C,7A,7B,7C, and are available in different density and package variants of Intel Stratix 10 devices.
Resolution
This problem is scheduled to be fixed in a future release of the Intel Quartus Prime Pro Edition Software.