Article ID: 000076737 Content Type: Troubleshooting Last Reviewed: 10/22/2020

Why does the 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example simulation run hang?

Environment

  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition version 20.1 Software, the design example generated by the 25G Ethernet Intel® Stratix® 10
    FPGA IP with dynamic reconfiguration and PTP enabled, will hang when simulated with either Synopsys* VCS* simulator or Cadence* Xcelium*/NCSIM* simulator. 

    Resolution

    To avoid this problem, user is encounraged to use Mentor* Modelsim* simulator to simulate the design example.

    This problem is fixed starting from the Intel® Quartus® Prime Pro Edition v20.3 software onwards.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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