Article ID: 000076728 Content Type: Product Information & Documentation Last Reviewed: 05/05/2021

How do I reconfigure an Intel® Arria® 10 and Intel® Cyclone® 10 I/O PLL with the PLL Reconfig IP when the I/O PLL cannot be locked?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • IOPLL Intel® FPGA IP
  • PLL Reconfig Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    PLL Reconfig IP currently checks IO PLL lock status before it allows reconfiguration to start. This causes the mgmt_wait_request to be asserted until the IO PLL achieves lock.

    Resolution

    To work around this problem, edit the .v file shown below in the project IP generated folder and change the parameter WAIT_FOR_LOCK value from 1 to 0. This will force the PLL Reconfig IP to not check the IOPLL lock status and de-assert the mgmt_waitrequest signal when core is ready.

    //synth/altera_pll_reconfig_top.v

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs

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