Description
When simulating the eSRAM Intel® FPGA IP targetting the Intel® Stratix® 10 devices with Mentor* ModelSim*, you may observe incorrect read data due to incorrect simulation options.
Resolution
To work around this problem, add the option below in the msim_setup.tcl file:
set USER_DEFINED_VERILOG_COMPILE_OPTIONS "+define+ESRAM_SIM"