Article ID: 000076619 Content Type: Troubleshooting Last Reviewed: 08/29/2012

What are the proper MSEL and VCCSEL configuration settings for Stratix II devices when VCCIO for I/O bank 3 is less than 2.5V?

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Description For boards designed with Stratix® II to power-up and configure correctly there are four cases to consider based on the Power On Reset (POR) trip point and configuration pin input buffers. For Passive Serial (PS) mode (MSEL[3,2,1,0] = 0010) and for Fast Passive Parallel (FPP) mode (MSEL[3,2,1,0] = 0000) the POR circuitry selects the trip point associated with 1.5V/1.8V signaling.  For all other configuration modes defined by MSEL[3,2,1,0] settings other than 00X0 (X = MSEL[1] = don't care), VCCSEL=GND selects the higher I/O Bank 3 POR trip point for 2.5V/3.3V signaling and VCCSEL=VCCPD selects the lower I/O Bank 3 POR trip point associated with 1.5V/1.8V signaling. The VCCSEL input pin also selects which input buffer is used during configuration. When VCCSEL = GND, the 3.3-V/2.5-V input buffer is selected and it is powered by VCCPD. When VCCSEL = VCCPD, the 1.8-V/1.5-V input buffer is selected and it is powered by VCCIO.

Case 1) With MSEL pins equal to 00X0 and VCCSEL = GND, configuration is supported from 3.3V down to 2.5V. The lower VCCIO3 POR trip point is selected. The 3.3-V/2.5-V input buffer is selected on configuration input pins.

Case 2) With MSEL pins equal to 00X0 and VCCSEL = VCCPD, configuration is supported from 3.3V down to 1.5V. The lower VCCIO3 POR trip point is selected. The 1.8-V/1.5-V input buffer is selected on configuration input pins and are 3.3V tolerant.

Case 3) With MSEL pins not equal to 00X0 and VCCSEL = GND, configuration is supported down from 3.3V down to 2.5V.  The higher VCCIO3 POR trip point is selected. The 3.3-V/2.5-V input buffer is selected on configuration input pins. VCCIO3 pins need to be powered by 3.3V or 2.5V for the device to exit POR and configure successfully.

Case 4) With MSEL pins not equal to 00X0 and VCCSEL = VCCPD, configuration is supported from 3.3V down to 1.5V. The lower VCCIO3 POR trip point is selected. The 1.8-V/1.5-V input buffer is selected on configuration input pins and are 3.3V tolerant.

The key is to ensure the VCCIO voltage of bank 3 is high enough to trip VCCIO POR trip point on power-up. Secondly, make sure the configuration device meets the VIH for the configuration input pins based on the selected input buffer. 

Note that Active Serial (AS) mode is only applicable for 3.3-V configuration. If I/O bank 3 is less than 3.3V then level shifters are required on the output pins from Stratix II device back to the EPCS device (DCLK, nCSO, ASDO).

The workaround for using less than 2.5V on I/O bank 3 when MSEL pins are not equal to 00X0 and VCCSEL = GND is to increase the VCCIO on bank 3 to a minimum of 2.375V until configuration is complete indicated by the CONF_DONE pin transitioning high. By adjusting the regulator to power bank 3 to the minimum requirement for 2.5V operation it will allow the device to configure. After configuration is complete you may lower the I/O bank 3 voltage back down to 1.8V, 1.5V, or 1.2V for device operation in user mode. Or you can switch to PS mode or FPP mode with MSEL[] pins = 00X0 if one of these modes is supported on your board.

POR trip points will occur below the minimum operating condition voltage as specified for 1.5V or 2.5V operation.

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This article applies to 2 products

Stratix® II GX FPGA
Stratix® II FPGAs

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