Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you will get the above error message when setting a negative phase shift on the output clock in the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.
Resolution
To work around the problem, set only positive phase shift for any output clocks inside the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.