Why does the Arria 10 RapidIO I & II IP Cores Generate Testbench result in error for input port connections?

The RapidIO I & II user guide recommends using the working example functional simulation testbench that is generated when IP  simulation model is generated. However, custers who would like to create their own testbench can use the "Generate Testbench System" option in Qsys.

During Qsys generation the error below will be seen:

"Error: <qsys system>_tb.<qsys system>_inst.tx_bonding_clocks_ch0: <qsys system>_inst.tx_bonding_clocks_ch0 must be connected to a hssi_bonded_clock output"

This error is expected. The Native PHY requires the tx_bonding_clock input port be connected to a Transceiver PLL output clock. The Generate Testbench simply creates a dummy wrapper to the IP cre and hence the error informs the user that ports need to be connected later in the final design.

To work around this problem:

1. Close the Generation dialog box.

2. In Quartus®, Go to "File" > "Open" > <qsys system>_tb > <qsys system>_tb.qsys

You will get Error message on the unconnected tx_bonding_clocks.

3. Export the tx_bonding_clocks ports to resolve the error.

4. Go to "Generate" > "Generate HDL..." > Simulation > select intended "Create simulation  model" > Generate

5. Done. You will get the simulation model same as from Generate testbench system.

This problem is not scheduled to be fix in a future release of the Quartus Prime software.