There are two new pin placement restrictions for the Arria® 10 Hard Processor System (HPS) EMIF IP starting in the Quartus® Prime Pro Edition Software version 19.2 related to PLL reference clock and RZQ pin placement. These restrictions are put into place to guarantee that all possible combinations of all supported configurations HPS EMIF IP usage will function correctly in hardware, including FPGA-First/HPS-First, x16/x32/x64 data widths, as well as ECC/Non-ECC operating modes. These restrictions are tighter than those implemented in previous versions of Quartus® Prime Software, therefore user may see new compilation errors for pinouts that used to pass compilation in earlier versions of Quartus® Prime Software. The error simply indicates that the existing pinout may not work across all combinations of supported HPS EMIF configurations. However, users with existing functional pinouts can continue to use the designs without concern if they do not intend to modify their configuration going forward.
In the Arria® 10 HPS EMIF interface, the PLL reference clock and RZQ pin must be placed in I/O bank 2K with the address and command signals.
Starting in the Quartus® Prime Pro Edition Software version 19.2, this restriction is implemented by reporting a fitter error during compilation if the pin placement requirements are not followed. Refer to the External Memory Interfaces Arria® 10 FPGA IP User Guide for more information regarding the HPS EMIF pin placement restrictions.
If you have a design that is currently passing compilation in a release earlier than the Quartus® Prime Pro Edition Software version 19.2 which fails in compilation in the Quartus® Prime Software Pro Edition Software version 19.2 and later, then you do not need to change the HPS EMIF design but will need a workaround.