Article ID: 000076455 Content Type: Troubleshooting Last Reviewed: 10/06/2020

Why does the Intel® Arria® 10 DDR4 IP not correct an ECC error?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Resolution

    A correctable bit error will not be corrected in the Intel® Arria® 10 DDR4 IP when a data mask does not correspond to a full byte (for example, a 4-bit data mask).
    This is because the ECC logic can only support read-modify-write on a byte-wide basis.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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