Article ID: 000076339 Content Type: Troubleshooting Last Reviewed: 03/16/2023

Why am I unable to use the Byte Enables for a True Dual-Port M9K memory block configured in a 32x8 mixed data width mode?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Byte Enables are not supported in this configuration due to the way that the memory gets implemented.

The widest port width supported in True Dual-Port Mode for a single M9K block is x18.  This means that a 32x8 bit memory actually gets implemented as two separate 16x4 bit M9K blocks.  Although in this scenario, each M9K block maintains it's 4:1 ratio, 4 bit wide byte enables are not supported.

Byte enables are only supported for True Dual-Port memory configurations when both the PortA and PortB data widths of the individual M9K memory blocks are multiples of 8 or 9 bits.

Resolution

N/A

Related Products

This article applies to 8 products

Cyclone® IV GX FPGA
Cyclone® IV E FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® III FPGAs
Cyclone® III LS FPGA
Cyclone® III FPGAs

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