Article ID: 000076335 Content Type: Troubleshooting Last Reviewed: 10/07/2020

Why does the awready signal from the AXI* Switch toggle when using Intel® Stratix® 10 MX HBM2 controller?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This is the expected behavior of the AXI* Switch when enabling pseudo BL8. The AXI* Switch needs to wait for the write data transfer of the transaction to complete before receiving the next write request. This will not impact the efficiency of the AXI* interface.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA

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