Article ID: 000076251 Content Type: Troubleshooting Last Reviewed: 11/28/2023

Why is the Slot Clock Configuration bit setting of the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express is always 0 regardless of the setting in the IP Catalog?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express and Avalon® -MM Intel® Stratix® 10 Hard IP for PCI Express in Intel® Quartus® Prime Pro Edition Software version 19.4, the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register is always set to 0. This problem can be seen in both simulation and hardware. 

    Resolution

    There is no workaround. 

    Related Products

    This article applies to 5 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 DX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 GX FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.