Article ID: 000076241 Content Type: Troubleshooting Last Reviewed: 03/18/2019

Why is the signal cmd_ready of the Temperature Sensor Intel® Stratix® 10 FPGA IP at high impedance state in simulation?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Temperature Sensor Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Temperature Sensor Intel® Stratix® 10 FPGA IP simulation model is not fully featured in the Intel® Quartus® Prime Pro Edition software. The output signal cmd_ready is at high impedance state (cmd_ready = 'bz) .

    Resolution

    The Temperature Sensor Intel® Stratix® 10 FPGA IP simulation model is scheduled to be updated in a future release of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs