Article ID: 000076149 Content Type: Error Messages Last Reviewed: 07/16/2013

Critical Warning (176575): Cannot implement Top/Bottom or Left/Right PLL <PLL name>, because the input clock of the PLL uses I/O standard LVDS and has a frequency of 800 MHz. However, the device only supports a frequency up to 762 MHz.

Environment

  • Quartus® II Subscription Edition
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    Description

    You will get this error when trying to assign a toggle rate of 800MHz or greater and a LVDS I/O assignment to a clock pin in Stratix® IV devices with densities of 820, 530, 360, and 290.

    Table 1-42 in the DC and Switching Characteristics for Stratix IV Devices (PDF) states that for a -2/-2X speed grade device, 800MHz is supported for fHSCLK_in (input clock frequency) True Differential I/O Standards.  This does not apply to the higher density devices listed above.  

    Resolution Table 1-42 is scheduled to be fixed to state that 762MHz is the maximum frequency supported in the higher density devices.

    Related Products

    This article applies to 3 products

    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® IV E FPGA

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