Article ID: 000076121 Content Type: Troubleshooting Last Reviewed: 12/16/2014

Why does the PCIe Gen3 testbench simulation not enter phase 2 or 3 of the equalization process?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Altera® testbench bus functional model (BFM) for the Hard IP for PCI Express® does not support simulation of phase 2 or phase 3 equalization.

Resolution

Use a third party BFM to simulate these equalization phases, which the Hard IP supports.

Related Products

This article applies to 3 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA